1. Field of the Invention
The present invention relates to a technology of a timing diagram editing in logic verification of a hardware module, and more particularly, to a technology of mathematically describing an interface protocol of a hardware module.
2. Description of the Related Art
Usually, in specifications regarding a hardware module, an interface protocol is described by combining an overall description mainly in natural language and an illustration of typical examples by a timing diagram. A general-use word processor and a timing diagram editing tool are used for preparation of such kind of specification.
Recently, technologies are provided for automatically generating a verification environment in performing logic verification of a hardware module by inputting a mathematical protocol description (for example, K. Ara and K. Suzuki, “A Proposal for Transaction-Level Verification with Component Wrapper Language”, in 2003 IEEE/ACM Design Automation and Test in Europe Conference and Exposition (DATE 2003), pp. 82-87, March 2003 or F. Balarin and R. Passerone, “Functional Verification Methodology Based on Formal Interface Specification and Transactor Generation”, in 2006 IEEE/ACM Design Automation and Test in Europe Conference and Exposition (DATE 2006), pp. 1013-1018, March 2006). These technologies employ text-based protocol description language based on “regular expression” in the formal language theory.
A graphic user interface (GUI) is provided that enables a logic designer to describe any arbitrary logic using a general-purpose timing diagram (for example, Japanese Patent Publication No. 3271522). According to this technology, a test case regarding logic design can automatically be generated on the GUI.
However, the conventional technologies described above require a user to have a special skill of freely writing and reading mathematical protocol description to be used. This led to a problem that a design work is very difficult for the user having no such skill, resulting in a prolonged design period.